Emulator PIO Registers¶
List of Registers¶
The PIO emulator provides registers in addition to those of the PIO as specified in the RP2040 datasheet to allow for inspection of more details of the PIO’s internal state such as its scratch registers X and Y, its shift registers ISR, OSR, FIFO memory, and read access to PIO instruction memory for enhanced debugging of programs. Base address for the two emulator PIO register sets (one register set for each of the two PIOs) is 0x58200000 and 0x58300000 for PIO0 and PIO1, respectively.
| Offset | Name | Info |
|---|---|---|
| 0x000 | SM0_REGX | Direct read / write access to the SM’s scratch register X. |
| 0x004 | SM0_REGY | Direct read / write access to the SM’s scratch register Y. |
| 0x008 | SM0_PC | Direct read / write access to the SM’s instruction pointer / program counter. |
| 0x00c | SM0_ISR | Direct read / write access to the SM’s input shift register. |
| 0x010 | SM0_ISR_SHIFT_COUNT | Direct read / write access to the SM’s input shift count register. |
| 0x014 | SM0_OSR | Direct read / write access to all of the SM’s output shift register. |
| 0x018 | SM0_OSR_SHIFT_COUNT | Direct read / write access to the SM’s output shift count register. |
| 0x01c | SM0_FIFO_MEM0 | Read / write access to FIFO memory word. |
| 0x020 | SM0_FIFO_MEM1 | Read / write access to FIFO memory word. |
| 0x024 | SM0_FIFO_MEM2 | Read / write access to FIFO memory word. |
| 0x028 | SM0_FIFO_MEM3 | Read / write access to FIFO memory word. |
| 0x02c | SM0_FIFO_MEM4 | Read / write access to FIFO memory word. |
| 0x030 | SM0_FIFO_MEM5 | Read / write access to FIFO memory word. |
| 0x034 | SM0_FIFO_MEM6 | Read / write access to FIFO memory word. |
| 0x038 | SM0_FIFO_MEM7 | Read / write access to FIFO memory word. |
| 0x03c | SM0_CLEAR_FORCED | When writing to this address, any pending forced instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x040 | SM0_CLEAR_EXECD | When writing to this address, any pending EXEC’d instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x044 | SM0_INSTR_ORIGIN | Direct read-only access to the origin of the SM’s currently executed instruction. The mode bits determine the origin category. If the origin category is memory address, the memory address bits will contain the memory instruction’s address. Otherwise, the bits of the memory address are undefined. Note that for memory instructions, the address may differ from the value of the instruction pointer PC, if the PC has already been updated while the instruction is still in progress. |
| 0x048 | SM0_DELAY | Direct read-only access to the SM’s currently executed instruction’s number of delay cycles. |
| 0x04c | SM0_DELAY_CYCLE | Read-only access to the SM’s delay status. |
| 0x050 | SM0_PENDING_DELAY | Direct read-only access to the SM’s number of pending delay cycles. |
| 0x054 | SM0_FORCED_INSTR | Direct read-only access to the op-code of a forced instruction that is awaiting execution during the next clock cycle. For writing a forced instruction, use SMx_INSTR of PIORegisters instead. |
| 0x058 | SM0_EXECD_INSTR | Direct read/write access to the op-code of an EXEC’d instruction that is awaiting execution during the next clock cycle, unless the state machine’s clock signal does not evaluate to true, or there is a pending forced instruction, in which case the forced instruction will be executed first. |
| 0x05c | SM0_CLK_ENABLE | Read-only access to the SM’s delay status. |
| 0x060 | SM0_BREAKPOINTS | Each bit of this value corresponds to each of the 32 memory locations of the PIO instruction memory (with the LSB of the word corresponding to the lowest memory address). Setting a bit to 1 marks the corresponding memory address as location of a breakpoint. Setting a bit to 0 removes the breakpoint. As soon as the program counter of the state machine reaches an address that is marked as a breakpoint, master clock MASTERCLK_MODE will be automatically set to single step mode. |
| 0x064 | SM0_TRACEPOINTS | Tracepoints work like breakpoints with the difference that master clock MASTERCLK_MODE it not automatically set to single step mode, but instead a message is typically printed to console output (depending on the specific client application). The message may, for example, caontain the state machine’s number and disassembled instruction with prefixed instruction memory address. Tracepoints work in all master clock MASTERCLK_MODE modes. |
| 0x068 | SM1_REGX | Direct read / write access to the SM’s scratch register X. |
| 0x06c | SM1_REGY | Direct read / write access to the SM’s scratch register Y. |
| 0x070 | SM1_PC | Direct read / write access to the SM’s instruction pointer / program counter. |
| 0x074 | SM1_ISR | Direct read / write access to the SM’s input shift register. |
| 0x078 | SM1_ISR_SHIFT_COUNT | Direct read / write access to the SM’s input shift count register. |
| 0x07c | SM1_OSR | Direct read / write access to all of the SM’s output shift register. |
| 0x080 | SM1_OSR_SHIFT_COUNT | Direct read / write access to the SM’s output shift count register. |
| 0x084 | SM1_FIFO_MEM0 | Read / write access to FIFO memory word. |
| 0x088 | SM1_FIFO_MEM1 | Read / write access to FIFO memory word. |
| 0x08c | SM1_FIFO_MEM2 | Read / write access to FIFO memory word. |
| 0x090 | SM1_FIFO_MEM3 | Read / write access to FIFO memory word. |
| 0x094 | SM1_FIFO_MEM4 | Read / write access to FIFO memory word. |
| 0x098 | SM1_FIFO_MEM5 | Read / write access to FIFO memory word. |
| 0x09c | SM1_FIFO_MEM6 | Read / write access to FIFO memory word. |
| 0x0a0 | SM1_FIFO_MEM7 | Read / write access to FIFO memory word. |
| 0x0a4 | SM1_CLEAR_FORCED | When writing to this address, any pending forced instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x0a8 | SM1_CLEAR_EXECD | When writing to this address, any pending EXEC’d instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x0ac | SM1_INSTR_ORIGIN | Direct read-only access to the origin of the SM’s currently executed instruction. The mode bits determine the origin category. If the origin category is memory address, the memory address bits will contain the memory instruction’s address. Otherwise, the bits of the memory address are undefined. Note that for memory instructions, the address may differ from the value of the instruction pointer PC, if the PC has already been updated while the instruction is still in progress. |
| 0x0b0 | SM1_DELAY | Direct read-only access to the SM’s currently executed instruction’s number of delay cycles. |
| 0x0b4 | SM1_DELAY_CYCLE | Read-only access to the SM’s delay status. |
| 0x0b8 | SM1_PENDING_DELAY | Direct read-only access to the SM’s number of pending delay cycles. |
| 0x0bc | SM1_FORCED_INSTR | Direct read-only access to the op-code of a forced instruction that is awaiting execution during the next clock cycle. For writing a forced instruction, use SMx_INSTR of PIORegisters instead. |
| 0x0c0 | SM1_EXECD_INSTR | Direct read/write access to the op-code of an EXEC’d instruction that is awaiting execution during the next clock cycle, unless the state machine’s clock signal does not evaluate to true, or there is a pending forced instruction, in which case the forced instruction will be executed first. |
| 0x0c4 | SM1_CLK_ENABLE | Read-only access to the SM’s delay status. |
| 0x0c8 | SM1_BREAKPOINTS | Each bit of this value corresponds to each of the 32 memory locations of the PIO instruction memory (with the LSB of the word corresponding to the lowest memory address). Setting a bit to 1 marks the corresponding memory address as location of a breakpoint. Setting a bit to 0 removes the breakpoint. As soon as the program counter of the state machine reaches an address that is marked as a breakpoint, master clock MASTERCLK_MODE will be automatically set to single step mode. |
| 0x0cc | SM1_TRACEPOINTS | Tracepoints work like breakpoints with the difference that master clock MASTERCLK_MODE it not automatically set to single step mode, but instead a message is typically printed to console output (depending on the specific client application). The message may, for example, caontain the state machine’s number and disassembled instruction with prefixed instruction memory address. Tracepoints work in all master clock MASTERCLK_MODE modes. |
| 0x0d0 | SM2_REGX | Direct read / write access to the SM’s scratch register X. |
| 0x0d4 | SM2_REGY | Direct read / write access to the SM’s scratch register Y. |
| 0x0d8 | SM2_PC | Direct read / write access to the SM’s instruction pointer / program counter. |
| 0x0dc | SM2_ISR | Direct read / write access to the SM’s input shift register. |
| 0x0e0 | SM2_ISR_SHIFT_COUNT | Direct read / write access to the SM’s input shift count register. |
| 0x0e4 | SM2_OSR | Direct read / write access to all of the SM’s output shift register. |
| 0x0e8 | SM2_OSR_SHIFT_COUNT | Direct read / write access to the SM’s output shift count register. |
| 0x0ec | SM2_FIFO_MEM0 | Read / write access to FIFO memory word. |
| 0x0f0 | SM2_FIFO_MEM1 | Read / write access to FIFO memory word. |
| 0x0f4 | SM2_FIFO_MEM2 | Read / write access to FIFO memory word. |
| 0x0f8 | SM2_FIFO_MEM3 | Read / write access to FIFO memory word. |
| 0x0fc | SM2_FIFO_MEM4 | Read / write access to FIFO memory word. |
| 0x100 | SM2_FIFO_MEM5 | Read / write access to FIFO memory word. |
| 0x104 | SM2_FIFO_MEM6 | Read / write access to FIFO memory word. |
| 0x108 | SM2_FIFO_MEM7 | Read / write access to FIFO memory word. |
| 0x10c | SM2_CLEAR_FORCED | When writing to this address, any pending forced instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x110 | SM2_CLEAR_EXECD | When writing to this address, any pending EXEC’d instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x114 | SM2_INSTR_ORIGIN | Direct read-only access to the origin of the SM’s currently executed instruction. The mode bits determine the origin category. If the origin category is memory address, the memory address bits will contain the memory instruction’s address. Otherwise, the bits of the memory address are undefined. Note that for memory instructions, the address may differ from the value of the instruction pointer PC, if the PC has already been updated while the instruction is still in progress. |
| 0x118 | SM2_DELAY | Direct read-only access to the SM’s currently executed instruction’s number of delay cycles. |
| 0x11c | SM2_DELAY_CYCLE | Read-only access to the SM’s delay status. |
| 0x120 | SM2_PENDING_DELAY | Direct read-only access to the SM’s number of pending delay cycles. |
| 0x124 | SM2_FORCED_INSTR | Direct read-only access to the op-code of a forced instruction that is awaiting execution during the next clock cycle. For writing a forced instruction, use SMx_INSTR of PIORegisters instead. |
| 0x128 | SM2_EXECD_INSTR | Direct read/write access to the op-code of an EXEC’d instruction that is awaiting execution during the next clock cycle, unless the state machine’s clock signal does not evaluate to true, or there is a pending forced instruction, in which case the forced instruction will be executed first. |
| 0x12c | SM2_CLK_ENABLE | Read-only access to the SM’s delay status. |
| 0x130 | SM2_BREAKPOINTS | Each bit of this value corresponds to each of the 32 memory locations of the PIO instruction memory (with the LSB of the word corresponding to the lowest memory address). Setting a bit to 1 marks the corresponding memory address as location of a breakpoint. Setting a bit to 0 removes the breakpoint. As soon as the program counter of the state machine reaches an address that is marked as a breakpoint, master clock MASTERCLK_MODE will be automatically set to single step mode. |
| 0x134 | SM2_TRACEPOINTS | Tracepoints work like breakpoints with the difference that master clock MASTERCLK_MODE it not automatically set to single step mode, but instead a message is typically printed to console output (depending on the specific client application). The message may, for example, caontain the state machine’s number and disassembled instruction with prefixed instruction memory address. Tracepoints work in all master clock MASTERCLK_MODE modes. |
| 0x138 | SM3_REGX | Direct read / write access to the SM’s scratch register X. |
| 0x13c | SM3_REGY | Direct read / write access to the SM’s scratch register Y. |
| 0x140 | SM3_PC | Direct read / write access to the SM’s instruction pointer / program counter. |
| 0x144 | SM3_ISR | Direct read / write access to the SM’s input shift register. |
| 0x148 | SM3_ISR_SHIFT_COUNT | Direct read / write access to the SM’s input shift count register. |
| 0x14c | SM3_OSR | Direct read / write access to all of the SM’s output shift register. |
| 0x150 | SM3_OSR_SHIFT_COUNT | Direct read / write access to the SM’s output shift count register. |
| 0x154 | SM3_FIFO_MEM0 | Read / write access to FIFO memory word. |
| 0x158 | SM3_FIFO_MEM1 | Read / write access to FIFO memory word. |
| 0x15c | SM3_FIFO_MEM2 | Read / write access to FIFO memory word. |
| 0x160 | SM3_FIFO_MEM3 | Read / write access to FIFO memory word. |
| 0x164 | SM3_FIFO_MEM4 | Read / write access to FIFO memory word. |
| 0x168 | SM3_FIFO_MEM5 | Read / write access to FIFO memory word. |
| 0x16c | SM3_FIFO_MEM6 | Read / write access to FIFO memory word. |
| 0x170 | SM3_FIFO_MEM7 | Read / write access to FIFO memory word. |
| 0x174 | SM3_CLEAR_FORCED | When writing to this address, any pending forced instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x178 | SM3_CLEAR_EXECD | When writing to this address, any pending EXEC’d instruction is cancelled, provided that instruction fetch & decode has not yet been started. |
| 0x17c | SM3_INSTR_ORIGIN | Direct read-only access to the origin of the SM’s currently executed instruction. The mode bits determine the origin category. If the origin category is memory address, the memory address bits will contain the memory instruction’s address. Otherwise, the bits of the memory address are undefined. Note that for memory instructions, the address may differ from the value of the instruction pointer PC, if the PC has already been updated while the instruction is still in progress. |
| 0x180 | SM3_DELAY | Direct read-only access to the SM’s currently executed instruction’s number of delay cycles. |
| 0x184 | SM3_DELAY_CYCLE | Read-only access to the SM’s delay status. |
| 0x188 | SM3_PENDING_DELAY | Direct read-only access to the SM’s number of pending delay cycles. |
| 0x18c | SM3_FORCED_INSTR | Direct read-only access to the op-code of a forced instruction that is awaiting execution during the next clock cycle. For writing a forced instruction, use SMx_INSTR of PIORegisters instead. |
| 0x190 | SM3_EXECD_INSTR | Direct read/write access to the op-code of an EXEC’d instruction that is awaiting execution during the next clock cycle, unless the state machine’s clock signal does not evaluate to true, or there is a pending forced instruction, in which case the forced instruction will be executed first. |
| 0x194 | SM3_CLK_ENABLE | Read-only access to the SM’s delay status. |
| 0x198 | SM3_BREAKPOINTS | Each bit of this value corresponds to each of the 32 memory locations of the PIO instruction memory (with the LSB of the word corresponding to the lowest memory address). Setting a bit to 1 marks the corresponding memory address as location of a breakpoint. Setting a bit to 0 removes the breakpoint. As soon as the program counter of the state machine reaches an address that is marked as a breakpoint, master clock MASTERCLK_MODE will be automatically set to single step mode. |
| 0x19c | SM3_TRACEPOINTS | Tracepoints work like breakpoints with the difference that master clock MASTERCLK_MODE it not automatically set to single step mode, but instead a message is typically printed to console output (depending on the specific client application). The message may, for example, caontain the state machine’s number and disassembled instruction with prefixed instruction memory address. Tracepoints work in all master clock MASTERCLK_MODE modes. |
| 0x1a0 | INSTR_MEM0 | Read / write access to instruction memory word. |
| 0x1a4 | INSTR_MEM1 | Read / write access to instruction memory word. |
| 0x1a8 | INSTR_MEM2 | Read / write access to instruction memory word. |
| 0x1ac | INSTR_MEM3 | Read / write access to instruction memory word. |
| 0x1b0 | INSTR_MEM4 | Read / write access to instruction memory word. |
| 0x1b4 | INSTR_MEM5 | Read / write access to instruction memory word. |
| 0x1b8 | INSTR_MEM6 | Read / write access to instruction memory word. |
| 0x1bc | INSTR_MEM7 | Read / write access to instruction memory word. |
| 0x1c0 | INSTR_MEM8 | Read / write access to instruction memory word. |
| 0x1c4 | INSTR_MEM9 | Read / write access to instruction memory word. |
| 0x1c8 | INSTR_MEM10 | Read / write access to instruction memory word. |
| 0x1cc | INSTR_MEM11 | Read / write access to instruction memory word. |
| 0x1d0 | INSTR_MEM12 | Read / write access to instruction memory word. |
| 0x1d4 | INSTR_MEM13 | Read / write access to instruction memory word. |
| 0x1d8 | INSTR_MEM14 | Read / write access to instruction memory word. |
| 0x1dc | INSTR_MEM15 | Read / write access to instruction memory word. |
| 0x1e0 | INSTR_MEM16 | Read / write access to instruction memory word. |
| 0x1e4 | INSTR_MEM17 | Read / write access to instruction memory word. |
| 0x1e8 | INSTR_MEM18 | Read / write access to instruction memory word. |
| 0x1ec | INSTR_MEM19 | Read / write access to instruction memory word. |
| 0x1f0 | INSTR_MEM20 | Read / write access to instruction memory word. |
| 0x1f4 | INSTR_MEM21 | Read / write access to instruction memory word. |
| 0x1f8 | INSTR_MEM22 | Read / write access to instruction memory word. |
| 0x1fc | INSTR_MEM23 | Read / write access to instruction memory word. |
| 0x200 | INSTR_MEM24 | Read / write access to instruction memory word. |
| 0x204 | INSTR_MEM25 | Read / write access to instruction memory word. |
| 0x208 | INSTR_MEM26 | Read / write access to instruction memory word. |
| 0x20c | INSTR_MEM27 | Read / write access to instruction memory word. |
| 0x210 | INSTR_MEM28 | Read / write access to instruction memory word. |
| 0x214 | INSTR_MEM29 | Read / write access to instruction memory word. |
| 0x218 | INSTR_MEM30 | Read / write access to instruction memory word. |
| 0x21c | INSTR_MEM31 | Read / write access to instruction memory word. |
| 0x220 | TXF0 | Direct read access to the TX FIFO for the corresponding state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_TXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. |
| 0x224 | TXF1 | Direct read access to the TX FIFO for the corresponding state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_TXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. |
| 0x228 | TXF2 | Direct read access to the TX FIFO for the corresponding state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_TXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. |
| 0x22c | TXF3 | Direct read access to the TX FIFO for the corresponding state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_TXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. |
| 0x230 | RXF0 | Direct write access to the RX FIFO for the corresponding state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_RXOVER error flag for this FIFO. |
| 0x234 | RXF1 | Direct write access to the RX FIFO for the corresponding state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_RXOVER error flag for this FIFO. |
| 0x238 | RXF2 | Direct write access to the RX FIFO for the corresponding state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_RXOVER error flag for this FIFO. |
| 0x23c | RXF3 | Direct write access to the RX FIFO for the corresponding state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_RXOVER error flag for this FIFO. |
| 0x240 | FREAD_PTR | Read pointers of all of the SM’s TX and RX FIFOs. |
| 0x244 | GPIO_PINS | Direct read / write access to all of the 32 GPIO pins. |
| 0x248 | GPIO_PINDIRS | Direct read / write access to all of the 32 GPIO pin directions. |
Emulator PIO Registers: SM0_REGX, SM1_REGX, SM2_REGX, SM3_REGX Registers¶
Offsets: 0x000, 0x068, 0x0d0, 0x138
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s scratch register X. | RW | 0 |
Emulator PIO Registers: SM0_REGY, SM1_REGY, SM2_REGY, SM3_REGY Registers¶
Offsets: 0x004, 0x06c, 0x0d4, 0x13c
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s scratch register Y. | RW | 0 |
Emulator PIO Registers: SM0_PC, SM1_PC, SM2_PC, SM3_PC Registers¶
Offsets: 0x008, 0x070, 0x0d8, 0x140
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s instruction pointer / program counter. | RW | 0 |
Emulator PIO Registers: SM0_ISR, SM1_ISR, SM2_ISR, SM3_ISR Registers¶
Offsets: 0x00c, 0x074, 0x0dc, 0x144
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s input shift register. | RW | 0 |
Emulator PIO Registers: SM0_ISR_SHIFT_COUNT, SM1_ISR_SHIFT_COUNT, SM2_ISR_SHIFT_COUNT, SM3_ISR_SHIFT_COUNT Registers¶
Offsets: 0x010, 0x078, 0x0e0, 0x148
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s input shift count register. | RW | 0 |
Emulator PIO Registers: SM0_OSR, SM1_OSR, SM2_OSR, SM3_OSR Registers¶
Offsets: 0x014, 0x07c, 0x0e4, 0x14c
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to all of the SM’s output shift register. | RW | 0 |
Emulator PIO Registers: SM0_OSR_SHIFT_COUNT, SM1_OSR_SHIFT_COUNT, SM2_OSR_SHIFT_COUNT, SM3_OSR_SHIFT_COUNT Registers¶
Offsets: 0x018, 0x080, 0x0e8, 0x150
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read / write access to the SM’s output shift count register. | RW | 0 |
Emulator PIO Registers: SM0_FIFO_MEM0, SM0_FIFO_MEM1, SM0_FIFO_MEM2, SM0_FIFO_MEM3, SM0_FIFO_MEM4, SM0_FIFO_MEM5, SM0_FIFO_MEM6, SM0_FIFO_MEM7, SM1_FIFO_MEM0, SM1_FIFO_MEM1, SM1_FIFO_MEM2, SM1_FIFO_MEM3, SM1_FIFO_MEM4, SM1_FIFO_MEM5, SM1_FIFO_MEM6, SM1_FIFO_MEM7, SM2_FIFO_MEM0, SM2_FIFO_MEM1, SM2_FIFO_MEM2, SM2_FIFO_MEM3, SM2_FIFO_MEM4, SM2_FIFO_MEM5, SM2_FIFO_MEM6, SM2_FIFO_MEM7, SM3_FIFO_MEM0, SM3_FIFO_MEM1, SM3_FIFO_MEM2, SM3_FIFO_MEM3, SM3_FIFO_MEM4, SM3_FIFO_MEM5, SM3_FIFO_MEM6, SM3_FIFO_MEM7 Registers¶
Offsets: 0x01c, 0x020, 0x024, 0x028, 0x02c, 0x030, 0x034, 0x038, 0x084, 0x088, 0x08c, 0x090, 0x094, 0x098, 0x09c, 0x0a0, 0x0ec, 0x0f0, 0x0f4, 0x0f8, 0x0fc, 0x100, 0x104, 0x108, 0x154, 0x158, 0x15c, 0x160, 0x164, 0x168, 0x16c, 0x170
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Read / write access to FIFO memory word. | RW | 0 |
Emulator PIO Registers: SM0_CLEAR_FORCED, SM1_CLEAR_FORCED, SM2_CLEAR_FORCED, SM3_CLEAR_FORCED Registers¶
Offsets: 0x03c, 0x0a4, 0x10c, 0x174
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | When writing to this address, any pending forced instruction is cancelled, provided that instruction fetch & decode has not yet been started. | WF | 0 |
Emulator PIO Registers: SM0_CLEAR_EXECD, SM1_CLEAR_EXECD, SM2_CLEAR_EXECD, SM3_CLEAR_EXECD Registers¶
Offsets: 0x040, 0x0a8, 0x110, 0x178
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | When writing to this address, any pending EXEC’d instruction is cancelled, provided that instruction fetch & decode has not yet been started. | WF | 0 |
Emulator PIO Registers: SM0_INSTR_ORIGIN, SM1_INSTR_ORIGIN, SM2_INSTR_ORIGIN, SM3_INSTR_ORIGIN Registers¶
Offsets: 0x044, 0x0ac, 0x114, 0x17c
Description
Direct read-only access to the origin of the SM’s currently executed instruction. The mode bits determine the origin category. If the origin category is memory address, the memory address bits will contain the memory instruction’s address. Otherwise, the bits of the memory address are undefined. Note that for memory instructions, the address may differ from the value of the instruction pointer PC, if the PC has already been updated while the instruction is still in progress.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:7 | Reserved. | ― | ― | ― |
| 6:5 | CATEGORY | For forced instructions, this is the value 3. For EXEC’d instructions, this is the value 2. Otherwise (e.g. after reset), this is the value 1. | RO | 1 |
| 4:0 | MEMORY_ADDRESS | memory address value (0x00…0x1f) | RO | 0 |
Emulator PIO Registers: SM0_DELAY, SM1_DELAY, SM2_DELAY, SM3_DELAY Registers¶
Offsets: 0x048, 0x0b0, 0x118, 0x180
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:5 | Reserved. | ― | ― | ― |
| 4:0 | ― | Direct read-only access to the SM’s currently executed instruction’s number of delay cycles. | RO | 0 |
Emulator PIO Registers: SM0_DELAY_CYCLE, SM1_DELAY_CYCLE, SM2_DELAY_CYCLE, SM3_DELAY_CYCLE Registers¶
Offsets: 0x04c, 0x0b4, 0x11c, 0x184
Description
Read-only access to the SM’s delay status.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:1 | Reserved. | ― | ― | ― |
| 0 | DELAY_CYCLE | 0x1, if the currently executed cycles is a delay cycle. | RO | 0 |
Emulator PIO Registers: SM0_PENDING_DELAY, SM1_PENDING_DELAY, SM2_PENDING_DELAY, SM3_PENDING_DELAY Registers¶
Offsets: 0x050, 0x0b8, 0x120, 0x188
Description
Direct read-only access to the SM’s number of pending delay cycles.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:5 | Reserved. | ― | ― | ― |
| 4:0 | PENDING_DELAY | Number (0x00…0x1f) of pending delays of the currently executed instruction. | RO | 0 |
Emulator PIO Registers: SM0_FORCED_INSTR, SM1_FORCED_INSTR, SM2_FORCED_INSTR, SM3_FORCED_INSTR Registers¶
Offsets: 0x054, 0x0bc, 0x124, 0x18c
Description
Direct read-only access to the op-code of a forced instruction that is awaiting execution during the next clock cycle. For writing a forced instruction, use SMx_INSTR of PIORegisters instead.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:17 | Reserved. | ― | ― | ― |
| 16 | PENDING | 0x1, if a forced instruction is awaiting execution, otherwise 0x0. | RO | 0 |
| 15:0 | INSTR | Instruction op-code, if any; otherwise, 0x0000. | RO | 0 |
Emulator PIO Registers: SM0_EXECD_INSTR, SM1_EXECD_INSTR, SM2_EXECD_INSTR, SM3_EXECD_INSTR Registers¶
Offsets: 0x058, 0x0c0, 0x128, 0x190
Description
Direct read/write access to the op-code of an EXEC’d instruction that is awaiting execution during the next clock cycle, unless the state machine’s clock signal does not evaluate to true, or there is a pending forced instruction, in which case the forced instruction will be executed first.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:17 | Reserved. | ― | ― | ― |
| 16 | PENDING | 0x1, if an EXEC’d instruction is awaiting execution, otherwise 0x0. | RO | 0 |
| 15:0 | INSTR | Instruction op-code, if any; otherwise, 0x0000. | RW | 0 |
Emulator PIO Registers: SM0_CLK_ENABLE, SM1_CLK_ENABLE, SM2_CLK_ENABLE, SM3_CLK_ENABLE Registers¶
Offsets: 0x05c, 0x0c4, 0x12c, 0x194
Description
Read-only access to the SM’s delay status.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:1 | Reserved. | ― | ― | ― |
| 0 | DELAY_CYCLE | 0x1, if in the current cycle the clock enable signal evaluates to 0x1. | RO | 0 |
Emulator PIO Registers: SM0_BREAKPOINTS, SM1_BREAKPOINTS, SM2_BREAKPOINTS, SM3_BREAKPOINTS Registers¶
Offsets: 0x060, 0x0c8, 0x130, 0x198
Description
Each bit of this value corresponds to each of the 32 memory locations of the PIO instruction memory (with the LSB of the word corresponding to the lowest memory address). Setting a bit to 1 marks the corresponding memory address as location of a breakpoint. Setting a bit to 0 removes the breakpoint.
As soon as the program counter of the state machine reaches an address that is marked as a breakpoint, master clock MASTERCLK_MODE will be automatically set to single step mode.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | BP_MEM31 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 30 | BP_MEM30 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 29 | BP_MEM29 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 28 | BP_MEM28 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 27 | BP_MEM27 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 26 | BP_MEM26 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 25 | BP_MEM25 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 24 | BP_MEM24 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 23 | BP_MEM23 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 22 | BP_MEM22 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 21 | BP_MEM21 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 20 | BP_MEM20 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 19 | BP_MEM19 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 18 | BP_MEM18 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 17 | BP_MEM17 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 16 | BP_MEM16 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 15 | BP_MEM15 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 14 | BP_MEM14 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 13 | BP_MEM13 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 12 | BP_MEM12 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 11 | BP_MEM11 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 10 | BP_MEM10 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 9 | BP_MEM9 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 8 | BP_MEM8 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 7 | BP_MEM7 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 6 | BP_MEM6 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 5 | BP_MEM5 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 4 | BP_MEM4 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 3 | BP_MEM3 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 2 | BP_MEM2 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 1 | BP_MEM1 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
| 0 | BP_MEM0 | 0x1, if the memory address is marked as breakpoint. | RW | 0 |
Emulator PIO Registers: SM0_TRACEPOINTS, SM1_TRACEPOINTS, SM2_TRACEPOINTS, SM3_TRACEPOINTS Registers¶
Offsets: 0x064, 0x0cc, 0x134, 0x19c
Description
Tracepoints work like breakpoints with the difference that master clock MASTERCLK_MODE it not automatically set to single step mode, but instead a message is typically printed to console output (depending on the specific client application). The message may, for example, caontain the state machine’s number and disassembled instruction with prefixed instruction memory address. Tracepoints work in all master clock MASTERCLK_MODE modes.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | TP_MEM31 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 30 | TP_MEM30 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 29 | TP_MEM29 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 28 | TP_MEM28 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 27 | TP_MEM27 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 26 | TP_MEM26 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 25 | TP_MEM25 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 24 | TP_MEM24 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 23 | TP_MEM23 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 22 | TP_MEM22 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 21 | TP_MEM21 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 20 | TP_MEM20 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 19 | TP_MEM19 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 18 | TP_MEM18 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 17 | TP_MEM17 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 16 | TP_MEM16 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 15 | TP_MEM15 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 14 | TP_MEM14 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 13 | TP_MEM13 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 12 | TP_MEM12 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 11 | TP_MEM11 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 10 | TP_MEM10 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 9 | TP_MEM9 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 8 | TP_MEM8 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 7 | TP_MEM7 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 6 | TP_MEM6 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 5 | TP_MEM5 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 4 | TP_MEM4 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 3 | TP_MEM3 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 2 | TP_MEM2 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 1 | TP_MEM1 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
| 0 | TP_MEM0 | 0x1, if the memory address is marked as tracepoint. | RW | 0 |
Emulator PIO Registers: INSTR_MEM0, INSTR_MEM1, INSTR_MEM2, INSTR_MEM3, INSTR_MEM4, INSTR_MEM5, INSTR_MEM6, INSTR_MEM7, INSTR_MEM8, INSTR_MEM9, INSTR_MEM10, INSTR_MEM11, INSTR_MEM12, INSTR_MEM13, INSTR_MEM14, INSTR_MEM15, INSTR_MEM16, INSTR_MEM17, INSTR_MEM18, INSTR_MEM19, INSTR_MEM20, INSTR_MEM21, INSTR_MEM22, INSTR_MEM23, INSTR_MEM24, INSTR_MEM25, INSTR_MEM26, INSTR_MEM27, INSTR_MEM28, INSTR_MEM29, INSTR_MEM30, INSTR_MEM31 Registers¶
Offsets: 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc, 0x1c0, 0x1c4, 0x1c8, 0x1cc, 0x1d0, 0x1d4, 0x1d8, 0x1dc, 0x1e0, 0x1e4, 0x1e8, 0x1ec, 0x1f0, 0x1f4, 0x1f8, 0x1fc, 0x200, 0x204, 0x208, 0x20c, 0x210, 0x214, 0x218, 0x21c
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Read / write access to instruction memory word. | RW | 0 |
Emulator PIO Registers: TXF0, TXF1, TXF2, TXF3 Registers¶
Offsets: 0x220, 0x224, 0x228, 0x22c
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct read access to the TX FIFO for the corresponding state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_TXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. | RF | ― |
Emulator PIO Registers: RXF0, RXF1, RXF2, RXF3 Registers¶
Offsets: 0x230, 0x234, 0x238, 0x23c
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:0 | ― | Direct write access to the RX FIFO for the corresponding state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_RXOVER error flag for this FIFO. | WF | 0 |
Emulator PIO Registers: FREAD_PTR Register¶
Offset: 0x240
Description
Read pointers of all of the SM’s TX and RX FIFOs.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31:28 | TXF0_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 27:24 | RXF0_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 23:20 | TXF1_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 19:16 | RXF1_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 15:12 | TXF2_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 11:8 | RXF2_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 7:4 | TXF3_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
| 3:0 | RXF3_READ_PTR | Offset (0…7) within FIFO memory for the next FIFO read operation | RO | 0 |
Emulator PIO Registers: GPIO_PINS Register¶
Offset: 0x244
Description
Direct read / write access to all of the 32 GPIO pins.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | GPIO_PIN31 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 30 | GPIO_PIN30 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 29 | GPIO_PIN29 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 28 | GPIO_PIN28 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 27 | GPIO_PIN27 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 26 | GPIO_PIN26 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 25 | GPIO_PIN25 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 24 | GPIO_PIN24 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 23 | GPIO_PIN23 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 22 | GPIO_PIN22 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 21 | GPIO_PIN21 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 20 | GPIO_PIN20 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 19 | GPIO_PIN19 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 18 | GPIO_PIN18 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 17 | GPIO_PIN17 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 16 | GPIO_PIN16 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 15 | GPIO_PIN15 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 14 | GPIO_PIN14 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 13 | GPIO_PIN13 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 12 | GPIO_PIN12 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 11 | GPIO_PIN11 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 10 | GPIO_PIN10 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 9 | GPIO_PIN9 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 8 | GPIO_PIN8 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 7 | GPIO_PIN7 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 6 | GPIO_PIN6 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 5 | GPIO_PIN5 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 4 | GPIO_PIN4 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 3 | GPIO_PIN3 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 2 | GPIO_PIN2 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 1 | GPIO_PIN1 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
| 0 | GPIO_PIN0 | 0x1 for HIGH or 0x0 for LOW | RW | 0 |
Emulator PIO Registers: GPIO_PINDIRS Register¶
Offset: 0x248
Description
Direct read / write access to all of the 32 GPIO pin directions.
| Bits | Name | Description | Type | Reset |
|---|---|---|---|---|
| 31 | GPIO_PINDIR31 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 30 | GPIO_PINDIR30 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 29 | GPIO_PINDIR29 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 28 | GPIO_PINDIR28 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 27 | GPIO_PINDIR27 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 26 | GPIO_PINDIR26 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 25 | GPIO_PINDIR25 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 24 | GPIO_PINDIR24 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 23 | GPIO_PINDIR23 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 22 | GPIO_PINDIR22 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 21 | GPIO_PINDIR21 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 20 | GPIO_PINDIR20 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 19 | GPIO_PINDIR19 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 18 | GPIO_PINDIR18 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 17 | GPIO_PINDIR17 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 16 | GPIO_PINDIR16 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 15 | GPIO_PINDIR15 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 14 | GPIO_PINDIR14 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 13 | GPIO_PINDIR13 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 12 | GPIO_PINDIR12 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 11 | GPIO_PINDIR11 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 10 | GPIO_PINDIR10 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 9 | GPIO_PINDIR9 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 8 | GPIO_PINDIR8 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 7 | GPIO_PINDIR7 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 6 | GPIO_PINDIR6 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 5 | GPIO_PINDIR5 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 4 | GPIO_PINDIR4 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 3 | GPIO_PINDIR3 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 2 | GPIO_PINDIR2 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 1 | GPIO_PINDIR1 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |
| 0 | GPIO_PINDIR0 | 0x1 for pin direction out or 0x0 for pin direction in | RW | 0 |