Emulator Global Registers¶

List of Registers¶

The PIO emulator provides global registers, hereafter called Emulator Global Registers, that are used to inspect and control the emulator as a whole (rather than just referring to a specifc PIO) and that are accessible through this registers facade and provided in addition to the registers of the original RP2040 hardware. Base address for the emulator global register set is 0x58000000.

Offset	Name	Info
0x000	PWR_UP	Writing the value 0xa55a5aa5 to this address will fully reset the emulator. Writing any other value will have no effect.
0x004	MASTERCLK_FREQ	Unsigned integer value that represents the target frequency of the emulation in 1/8Hz. That is, a value of 1 represents a frequency of 0.125 Hz, and the maximum value of 2^32 - 1 = 4294967295 represents a frequency of 536.870911875MHz. A value of 0 indicates that the emulation should execute as fast as possible. Note that there is no guarantee at all to run at the specified frequency. Instead, the value is just the frequency that the emulation tries to catch up with as close as possible. The reset value corresponds to a target frequency of 125MHz.
0x008	MASTERCLK_MODE	Selects the clock mode.
0x00c	MASTERCLK_TRIGGER_PHASE0	When master clock is in single step mode, writing any value to this address will trigger the emulator to execute phase 0 of the next clock cycle. In phase 0, the emulator fetches and decodes the next instruction. When already in phase 0, writing once more to this address will have no effect. When master clock is in target frequency mode, writing to this address will have no effect. Upon reset, the system is in phase 1. Reading from this register will return value 0x1 if and only if the emulator is in phase 0 and phase 0 is settled (i.e. the emulator has completed all operations to be performed during this phase), and 0x0 otherwise.
0x010	MASTERCLK_TRIGGER_PHASE1	When master clock is in single step mode, writing any value to this address will trigger the emulator to execute phase 1 of the current clock cycle. In phase 1, the emulator will execute the instruction previously decoded in phase 0. When already in phase 1, writing once more to this address will have no effect. When master clock is in target frequency mode, writing to this address will have no effect. Upon reset, the system is in phase 1. Reading from this register will return value 0x1 if and only if the emulator is in phase 1 and phase 1 is settled (i.e. the emulator has completed all operations to be performed during this phase), and 0x0 otherwise.
0x014	WALLCLOCK_LSB	LSB value (lower 32 bits) of wall clock. The wall clock is a 64 bit counter that is initialized to 0 and incremented whenever the master clock has completed a cycle.
0x018	WALLCLOCK_MSB	MSB value (upper 32 bits) of wall clock. The wall clock is a 64 bit counter that is initialized to 0 and incremented whenever the master clock has completed a cycle.
0x01c	GPIO_PINS	Each bit of this value corresponds to each of the 32 GPIO pins’ pad input state that is provided from some external source.

Emulator Global Registers: PWR_UP Register¶

Offset: 0x000

Bits	Name	Description	Type	Reset
31:0	―	Writing the value 0xa55a5aa5 to this address will fully reset the emulator. Writing any other value will have no effect.	WF	0

Emulator Global Registers: MASTERCLK_FREQ Register¶

Offset: 0x004

Bits	Name	Description	Type	Reset
31:0	―	Unsigned integer value that represents the target frequency of the emulation in 1/8Hz. That is, a value of 1 represents a frequency of 0.125 Hz, and the maximum value of 2^32 - 1 = 4294967295 represents a frequency of 536.870911875MHz. A value of 0 indicates that the emulation should execute as fast as possible. Note that there is no guarantee at all to run at the specified frequency. Instead, the value is just the frequency that the emulation tries to catch up with as close as possible. The reset value corresponds to a target frequency of 125MHz.	RW	1000000000

Emulator Global Registers: MASTERCLK_MODE Register¶

Offset: 0x008

Description

Selects the clock mode.

Bits	Name	Description	Type	Reset
31:1	Reserved.	―	―	―
0	―	Bit 0 = 0: Target frequency mode. Bit 0 = 1: Single step mode.	RW	0

Emulator Global Registers: MASTERCLK_TRIGGER_PHASE0 Register¶

Offset: 0x00c

Bits	Name	Description	Type	Reset
31:0	―	When master clock is in single step mode, writing any value to this address will trigger the emulator to execute phase 0 of the next clock cycle. In phase 0, the emulator fetches and decodes the next instruction. When already in phase 0, writing once more to this address will have no effect. When master clock is in target frequency mode, writing to this address will have no effect. Upon reset, the system is in phase 1. Reading from this register will return value 0x1 if and only if the emulator is in phase 0 and phase 0 is settled (i.e. the emulator has completed all operations to be performed during this phase), and 0x0 otherwise.	WF	―

Emulator Global Registers: MASTERCLK_TRIGGER_PHASE1 Register¶

Offset: 0x010

Bits	Name	Description	Type	Reset
31:0	―	When master clock is in single step mode, writing any value to this address will trigger the emulator to execute phase 1 of the current clock cycle. In phase 1, the emulator will execute the instruction previously decoded in phase 0. When already in phase 1, writing once more to this address will have no effect. When master clock is in target frequency mode, writing to this address will have no effect. Upon reset, the system is in phase 1. Reading from this register will return value 0x1 if and only if the emulator is in phase 1 and phase 1 is settled (i.e. the emulator has completed all operations to be performed during this phase), and 0x0 otherwise.	WF	―

Emulator Global Registers: WALLCLOCK_LSB Register¶

Offset: 0x014

Bits	Name	Description	Type	Reset
31:0	―	LSB value (lower 32 bits) of wall clock. The wall clock is a 64 bit counter that is initialized to 0 and incremented whenever the master clock has completed a cycle.	RO	―

Emulator Global Registers: WALLCLOCK_MSB Register¶

Offset: 0x018

Bits	Name	Description	Type	Reset
31:0	―	MSB value (upper 32 bits) of wall clock. The wall clock is a 64 bit counter that is initialized to 0 and incremented whenever the master clock has completed a cycle.	RO	―

Emulator Global Registers: GPIO_PINS Register¶

Offset: 0x01c